1. Technical Field
Example embodiments relate to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices having metal gate electrodes.
2. Description of the Related Art
According to a conventional process for forming the metal gate electrode of semiconductor devices, a dummy gate structure is formed on a substrate and an interlayer insulating layer is formed on the substrate to cover the dummy gate structure. Then, the interlayer insulating layer may be partially removed from the substrate by a planarization process in such a way that only the dummy gate structure is exposed. Thereafter, the dummy gate structure may be replaced with conductive metal by a replacement metal gate (RMG) process, to thereby form the metal gate electrode of the semiconductor device.
The interlayer insulating layer is formed on a whole surface of the substrate including an edge area as well as a pattern area of the substrate, and the interlayer insulating layer at the edge area of the substrate still remains while the dummy gate structure is removed by the RMG process at the pattern area of the substrate. Therefore, the edge area of the substrate is protected from an etching of the RMG process at the pattern area by the interlayer insulating layer. For example, the edge area is protected from the etching process while removing the dummy gate structure from the pattern area in the RMG process.
However, there has been found that the interlayer insulating layer may be partially removed from the edge area of the substrate in the planarization process. In such a case, the edge area of the substrate may also be etched off in the RMG process, and an edge trench may be formed together with the removal of the dummy gate structure at the pattern area.
When conductive materials is filled up into the edge trench in a following metal gate process and a wiring process, the conductive bulk in the edge trench functions as a defect source of the semiconductor device.